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| DRAM MODULE KMM5322200C2W/C2WG 2Mx32 DRAM SIMM (1MX16 Base) Revision 0.0 November 1997 -1- Rev. 0.0 (Nov. 1997) DRAM MODULE Revision History Version 0.0 (November 1997) * Changed module PCB from 6-Layer to 4-Layer. KMM5322200C2W/C2WG * Changed Module Part No. from KMM5322200CW/CWG to KMM5322200C2W/C2WG caused by PCB revision . -2- Rev. 0.0 (Nov. 1997) DRAM MODULE KMM5322200C2W/C2WG with Fast Page Mode 2M x 32 DRAM SIMM using 1Mx16, 1K Refresh, 5V GENERAL DESCRIPTION The Samsung KMM5322200C2W is a 2Mx32bits Dynamic RAM high density memory module. The Samsung KMM5322200C2W consists of four CMOS 1Mx16bits DRAMs in 42-pin SOJ packages mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM5322200C2W is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. KMM5322200C2W/C2WG FEATURES * Part Identification - KMM5322200C2W(1024 cycles/16ms Ref, SOJ, Solder) - KMM5322200C2WG(1024 cycles/16ms Ref, SOJ, Gold) * Fast Page Mode Operation * CAS-before-RAS refresh capability * RAS-only refresh capability * TTL compatible inputs and outputs * Single +5V 10% power supply * JEDEC standard PDPin & pinout * PCB : Height(750mil), double sided component PERFORMANCE RANGE Speed -5 -6 tRAC 50ns 60ns tCAC 15ns 15ns tRC 90ns 110ns PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc NC A0 A1 A2 A3 A4 A5 A6 Res(A10) DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 Res(A11) Vcc A8 A9 RAS1 RAS0 NC NC Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol NC NC Vss CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 Vcc DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC Vss PIN NAMES Pin Name A0 - A9 DQ0 - DQ31 W RAS0 , RAS1 CAS0 - CAS3 PD1 -PD4 Vcc Vss NC Res Function Address Inputs Data In/Out Read/Write Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5V) Ground No Connection Reserved Pin PRESENCE DETECT PINS (Optional) Pin PD1 PD2 PD3 PD4 50NS NC NC Vss Vss 60NS NC NC NC NC * Pin connection changing available SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -3- Rev. 0.0 (Nov. 1997) DRAM MODULE FUNCTIONAL BLOCK DIAGRAM KMM5322200C2W/C2WG DQ0-DQ15 RAS0 RAS U0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 U2 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0-A9 RAS RAS1 CAS0 LCAS LCAS CAS0 CAS1 UCAS UCAS CAS1 OE OE A0-A9 W W DQ16-DQ31 RAS U1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 U3 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0-A9 RAS CAS2 LCAS LCAS CAS2 CAS3 UCAS UCAS CAS3 OE A0-A9 W OE W A0-A9 W Vcc .1 or .22uF Capacitor for each DRAM Vss To all DRAMs -4- Rev. 0.0 (Nov. 1997) DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative to V SS Voltage on V CC supply relative to V SS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg Pd IOS KMM5322200C2W/C2WG Rating -1 to +7.0 -1 to +7.0 -55 to +150 4 50 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to V SS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage *1 : VCC+2.0V/20ns, Pulse width is measured at VCC. *2 : -2.0V/ 20ns, Pulse width is measured at VSS. Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0 *2 Typ 5.0 0 Max 5.5 0 VCC+1 *1 0.8 Unit V V V V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM5322200C2W/C2WG Min - Max 304 284 8 304 284 184 164 4 304 284 20 10 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V -20 -10 2.4 - : Operating Current * ( RAS, LCAS or UCAS, Address cycling @ tRC=min) : Standby Current ( RAS=LCAS=UCAS=W=VIH) : RAS Only Refresh Current * ( LCAS=UCAS=VIH, RAS cycling @ tRC=min) : Fast Page Mode Current * ( RAS=VIL, LCAS or UCAS cycling : tPC=min) : Standby Current ( RAS=LCAS=UCAS=W=Vcc-0.2V) : CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @ tRC=min) : Input Leakage Current (Any input 0 VINVcc+0.5V, all other pins not under test=0 V) : Output Leakage Current(Data Out is disabled, 0V VOUTVcc) : Output High Voltage Level (I OH = -5mA) : Output Low Voltage Level (I OL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle, tPC. -5- Rev. 0.0 (Nov. 1997) DRAM MODULE CAPACITANCE (TA = 25C, VCC=5V, f = 1MHz) Item Input capacitance[A0-A9] Input capacitance[ W] Input capacitance[ RAS0 , RAS1] Input capacitance[ CAS0 - CAS3] Input/Output capacitance[DQ0-31] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min - KMM5322200C2W/C2WG Max 35 45 40 30 30 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, V oh/Vol=2.4/0.4V, Output loading CL=100pF Parameter Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time CAS setup time( CAS-before-RAS refresh) CAS hold time( CAS-before-RAS refresh) RAS precharge to CAS hold time Access time from CAS precharge Symbol -5 Min 90 50 13 25 0 0 3 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 13 13 0 10 16 0 5 10 5 30 0 5 10 5 35 10K 37 25 10K 15 50 0 0 3 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 0 10 16 10K 45 30 10K 15 50 Max Min 110 60 15 30 -6 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns 3 7 9 9 8 8 4 10 3,4 3,4,5 3,10 3 6 2 Note tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCPA -6- Rev. 0.0 (Nov. 1997) DRAM MODULE Test condition : Vih/Vil=2.4/0.8V, V oh/Vol=2.4/0.4V, Output loading CL=100pF Parameter Fast page mode cycle time CAS precharge time(Fast page cycle) RAS pulse width(Fast page cycle) W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Symbol -5 Min 35 10 50 10 10 200K Max KMM5322200C2W/C2WG AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) -6 Min 40 10 60 10 10 200K Max Unit ns ns ns ns ns Note tPC tCP tRASP tWRP tWRH NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and V IL(max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and V IL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristic s only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameter are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. -7- Rev. 0.0 (Nov. 1997) DRAM MODULE READ CYCLE KMM5322200C2W/C2WG tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tAA tCAC tCLZ DATA-OUT tOFF DQ VOH VOL - tRAC OPEN Dont care Undefined -8- Rev. 0.0 (Nov. 1997) DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM5322200C2W/C2WG tRAS RAS VIH VIL - tRC tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined -9- Rev. 0.0 (Nov. 1997) DRAM MODULE FAST PAGE READ CYCLE NOTE : DOUT = OPEN KMM5322200C2W/C2WG tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCSH tCAH COLUMN ADDRESS tCP tCAS o tCP tRSH tCAS tASR A VIH VIL ROW ADDR tRAH tASC tCAH o o tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tRCS o tRCS tRCH tCAC tAA tRAC tCLZ VALID DATA-OUT tCAC tAA tOFF tCLZ VALID DATA-OUT tCAC tAA tOFF tCLZ VALID DATA-OUT tOFF DQ VOH VOL - Dont care Undefined - 10 - Rev. 0.0 (Nov. 1997) DRAM MODULE FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM5322200C2W/C2WG tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCP tCAS o tPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCSH tCAH COLUMN ADDRESS tASC tCAH o o tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWP tCWL tWCS tWP tCWL tDS tWCH o tWCS tWCH tWP tCWL tRWL tDH tDS DQ VIH VIL - tDH tDH o tDS VALID DATA-IN VALID DATA-IN o VALID DATA-IN Dont care Undefined - 11 - Rev. 0.0 (Nov. 1997) DRAM MODULE RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Don't care DOUT = OPEN tRC KMM5322200C2W/C2WG tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRPC tCRP tASR A VIH VIL ROW ADDR tRAH CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don't care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWRP tWRH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined - 12 - Rev. 0.0 (Nov. 1997) DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM5322200C2W/C2WG tRC tRAS RAS VIH VIL - tRC tRP tRAS tRP tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tRCS W VIH VIL - tRRH tWRP tAA tCAC tCLZ DATA-OUT tOFF tRAC DQ VOH VOL - OPEN Dont care Undefined - 13 - Rev. 0.0 (Nov. 1997) DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN KMM5322200C2W/C2WG tRC RAS VIH VIL - tRC tRP tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRAD tRSH tCHR tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tWRP W VIH VIL - tWCS tWP tWCH tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined - 14 - Rev. 0.0 (Nov. 1997) DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE KMM5322200C2W/C2WG tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W VIH VIL - tWRP tWRH tRCS tAA tCAC tRRH tRCH DQ VOH VOL - tCLZ DATA-OUT tOFF WRITE CYCLE W VIH VIL - tWRP tWRH tWCS tRWL tCWL tWCH tWP tDS tDH DATA-IN DQ VIH VIL - OPEN Dont care Undefined NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. - 15 - Rev. 0.0 (Nov. 1997) DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care KMM5322200C2W/C2WG tRP RAS VIH VIL - tRASS tRPS tRPC tCHS tRPC tCP CAS VIH VIL - tCSR tOFF DQ VOH VOL - OPEN tWRP tWRH W VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Dont care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWTS tWTH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined - 16 - Rev. 0.0 (Nov. 1997) DRAM MODULE PACKAGE DIMENSIONS KMM5322200C2W/C2WG Units : Inches (millimeters) 4.250(107.95) 3.984(101.19) .133(3.38) R.062(1.57) .125 DIA.002(3.18.051) .400(10.16) .750(19.05) .250(6.35) .080(2.03) .250(6.35) .250(6.35) 3.750(95.25) R.062.004(R1.57.10) .125(3.17) MIN ( Front view ) ( Back view ) Gold & Solder Plating Lead .350(8.89) MAX .010(.25)MAX .100(2.54) MIN .225(5.71) MIN .050(1.27) .041.004(1.04.10) .054(1.37) .047(1.19) Tolerances : .005(.13) unless otherwise specified NOTE : The used device is 1Mx16 DRAM DRAM Part No. : KMM5322200C2W/C2WG -- KM416C1200CJ (400 mil) Revision History Rev 0.0 : Nov. 1997 - 17 - Rev. 0.0 (Nov. 1997) |
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